QuickLogic has patented an efficient input terminated readable and resettable configuration memory latch. The latch includes pull-up and pull-down networks, reset functionality, and a scan mode input for automated testing of programmable logic devices. The sensing block allows for reading the state of the bit line. GlobalData’s report on QuickLogic gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on QuickLogic, was a key innovation area identified from patents. QuickLogic's grant share as of April 2024 was 87%. Grant share is based on the ratio of number of grants to total number of patents.
Configuration memory latch with input terminated readable and resettable
A recently granted patent (Publication Number: US11935618B2) discloses a configuration memory latch designed for use in integrated circuits, specifically programmable logic devices (PLDs) and field programmable gate arrays (FPGAs). The latch comprises a complex network of pMOS and nMOS transistors arranged in pull-up and pull-down configurations, controlled by reset, write, and read signals. The latch allows for data to be written and read, with the state of the bit line (BL) indicating the stored data during read operations. Additionally, a scan mode input is included to facilitate testing using Automatic Test Pattern Generator (ATPG) tools, ensuring the reliability and functionality of the configuration memory latch within the IC.
Furthermore, the patent details the initiation of a new reset cycle before each write operation, ensuring the latch is in a consistent state. The presence of a word line read (WLR) signal enables data to be read from the latch, with a sensing block facilitating the interpretation of the BL state during read operations. The configuration memory latch is designed to be versatile, forming a crucial component of PLDs and FPGAs, providing a reliable and efficient means of storing and retrieving data within the integrated circuit. The inclusion of various transistors, inverters, and control signals highlights the complexity and precision required in the design and operation of such memory latches, ensuring optimal performance and functionality within the IC environment.
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