Synopsys has been granted a patent for a memory transparent in-system built-in self-test method. The technology involves testing subsets of memory cells over test intervals, copying contents to registers, writing test data, reading back contents, and restoring content. The system precludes functional circuitry access during testing. GlobalData’s report on Synopsys gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Synopsys, AI assisted CAD was a key innovation area identified from patents. Synopsys's grant share as of May 2024 was 48%. Grant share is based on the ratio of number of grants to total number of patents.
Memory transparent in-system built-in self-test for integrated circuits
A recently granted patent (Publication Number: US12002530B2) discloses an integrated circuit (IC) device featuring a memory system with multiple memory cells, control circuitry that prevents functional circuitry from accessing memory cells during test sessions, one or more registers, and memory built-in self-test (MBIST) circuitry. The MBIST circuitry is designed to test subsets of memory cells during test sessions by storing contents of the subsets in registers before testing and restoring them afterward. The patent also details the configuration of the MBIST circuitry to test overlapping sets of memory blocks, copy contents to registers, and manage non-overlapping portions efficiently.
Furthermore, the patent outlines a method associated with the IC device, emphasizing the preclusion of functional circuitry from accessing memory cells during test sessions and the testing of memory cell subsets using MBIST circuitry. The method involves storing contents in registers before testing and restoring them afterward, along with testing overlapping sets of memory blocks and managing non-overlapping portions effectively. The patent highlights the flexibility of the MBIST circuitry, allowing for the configuration of multiple registers and the testing of various memory cell configurations, enhancing the efficiency and accuracy of memory testing processes within the IC device.
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